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CS5106
CS5106
Multi-Feature, Synchronous plus Auxiliary PWM Controller
Description
The CS5106 is a fixed frequency, current mode controller with one single NFET driver and one dual FET, synchronous driver. The synchronous driver allows for increased efficiency of the main isolated power stage and the single driver allows the designer to develop auxiliary supplies for controller power as well as secondary side house keeping. In addition, because the synchronous drivers have programmable FET non-overlap, the CS5106 is an ideal controller for soft-switched converter topologies. The CS5106 is specifically designed for isolated topologies where speed, flexibility, reduced size and reduced component count are requirements. The controller contains the following features: Undervoltage Shutdown, Overvoltage Shutdown, Programmable Frequency, Programmable Synchronous NonOverlap Time, Master/Slave Clocking with Frequency Range Detection, Enable, Output Undervoltage Protection with Timer, 20mA 5V Output, 80ns PWM propagation delay, and Controlled Hiccup Mode. The CS5106 has junction temperature and supply ranges of -40uC to 125uC and 9V to 16V respectively and is available in the 24 lead SSOP package.
Features
s Programmable Fixed Frequency s Programmable FET Nonoverlap s Enable Lead s 12V Fixed Auxiliary Supply Control s Under and Overvoltage Shutdown s Output Undervoltage Protection with Timer s Master/Slave Clock Syncing Capability s Sync Frequency Range Detection s 80ns PWM Propagation Delay s 20mA 5V Reference Output s Small 24 lead SSOP Package s Controlled Hiccup Mode
Applications Diagram 48V to 3.3V Forward Converter with Synchronous Rectifiers
VIN R27 R1 VAUXP R3 R2 R4 C3 SYNCIN ENABLE
V5REF
CS5106
UVSD ENABLE PROGRAM OVSD V5REF SYNC IN SYNC OUT OAM OAOUT FADJ OUVDELAY DLYSET ILIM2 ILIM1 RAMP2 RAMP1 VFB1 VFB2 VSS GATE2B VCC GATE2 VDD GATE1
SYNCOUT C6 R24 D8 R25 R14 C8 R13 R9 T4
CNY17-4
C1 C2
D5 R7 R20 R15 R16 C14 R17 C13 R18
Package Options
24 Lead SSOP
UVSD
1
VAUXP D1 T1 C4
TL431 VAUXS Q7
R19
VIN VIN R8
ENABLE PROGRAM SYNCIN SYNCOUT FADJ DLYSET ILIM2 RAMP2 VFB2 GATE2B GATE2 VDD
OVSD V5REF OAM OAOUT
L1 Q5 Q3 Q4
C5
D2 Q1
D3 Q2 C9 C10 R10 VIN R11 R26 Q6 T2 T3 R12 D4 D7 R23 C11 VMAIN C12 R21
R5 VAUXS C7
OUVDELAY ILIM1 RAMP1 VFB1 VSS VCC GATE1
R6
D6
R22
Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com
Rev. 10/27/98
1
A
Company
CS5106
Absolute Maximum Ratings Operating Junction Temperature, TJ ..................................................................................................................................... 150C Operating Temperature Range, TA ...............................................................................................................................-40 to 85C Storage Temperature Range, TS ...................................................................................................................................-65 to 150C ESD (Human Body Model).........................................................................................................................................................2kV Lead Temperature Soldering: Reflow (SMD styles only).............................................60 sec. max above 183C, 230C peak VMAX 6V 6V 6V 6V 6V 6V 6V 6V 6V 20V 20V 20V 0V 20V 20V 6V 6V 6V 2.5V 2.5V 6V 6V 16V 16V VMIN -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V 0V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V ISOURCE 1mA 1mA 150mA 250A 300A 15A 10A 10A 5A 2A See Note 1 0.5A Peak 100mA DC 0.5A Peak 0.5A Peak 100mA DC 0.5A Peak 100mA DC 10A 10A 10A 125A 125A 50mA N/A 30A 300A ISINK N/A N/A 25mA 1.2mA 100mA N/A N/A N/A 100A 0.5A Peak 300mA DC 0.5A Peak 300mA DC 0.5Peak 100mA DC N/A 300mA DC 0.5APeak 100mA DC 0.5A Peak 100mA DC 100A N/A N/A N/A N/A 100mA 1mA N/A N/A
Lead Symbol
Lead Name
UVSD OVSD V5REF OAM OAOUT OUVDELAY ILIM1 RAMP1 VFB1 VSS VCC GATE1 Gnd GATE2 GATE2B VFB2 RAMP2 ILIM2 DLYSET FADJ SYNCOUT SYNCIN PROGRAM ENABLE
Undervoltage Shutdown Input Overvoltage Shutdown Input 5V Reference Output Error Amp Minus Input Error Amp Output Output Overcurrent Timer Capacitor Auxiliary Primary Side Current Limit Input Auxiliary Primary Side Current Ramp Input Auxiliary Voltage Feedback Input Bootstrapped Power Input Main Power Input Auxiliary FET Driver Output Ground Synchronous FET Driver Output Synchronous FET Driver Output B Synchronous Voltage Feedback Input Synchronous Primary Side Current Ramp Input Synchronous Primary Side Current Limit Input Gate Non-Overlap Programming Input Frequency Programming Input Clock Master Output Clock Slave Input Enable Programming Input Enable Input
Note 1: Current out of VCC is not limited. Care should be taken to prevent shorting VCC to Ground.
2
CS5106
Electrical Characteristics: TJ = -40C to 125C, VSS = 9 to 16V, V5REF ILOAD = 2mA, SYNCOUT Free Running, unless otherwise specified. For All Specs: UVSD=6V, OVSD = 0V, ENABLE = 0V, ILIM(1,2) = 0,VFB(1,2) = 3V,RFADJ = RDLYSET = 27.4k1/2.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
s VSS Supply Current
Measure current into VSS when V5REF ILOAD=0mA. 9V VSS 13V. Measure current into VSS when V5REF ILOAD=0mA. 13V < VSS 16V. Measure current into VSS when V5REF ILOAD=0mA. 16V < VSS 20V. Float VSS. Set VCC=7V & measure VCC current while V5REF ILOAD=0mA.
16.00 16.00 16.00
23.00 25.00 30.00
mA mA mA
s Low VCC Supply Current
1.50
3.50
mA
s VSS TO VCC DIODE Diode ON Voltage s Reference 5V Internal Voltage Reference VREFOK Threshold
Measure VSS - VCC.
0.20
0.75
1.00
V
Measure VREF voltage when IREF=0 and IREF=20 mA. Adjust VREF from 4.8V-4.0V until PWM1,2 goes low.
4.85 4.30
5.00 4.55
5.15 4.70
V V
s Low VCC Lockout VCC Turnon Threshold Voltage VCC Turnoff Threshold Voltage Hysteresis s Clock Operating Frequency1 SYNCIN Input Impedance SYNCOUT Output Low Voltage SYNCOUT Output High Voltage SYNCIN Detect Frequency
VCC increasing until ICC > 3.5mA V5REF ILOAD = 0mA VCC decreasing until ICC < 3.5mA V5REF ILOAD = 0mA Turnon - Turnoff
7.00 6.30 0.40
7.25 6.70 0.55
7.50 7.10 0.70
V V V
Measure frequency from SYNCOUT. Measure input impedance. RLOAD = 2k1/2 to V5REF RLOAD = 2k1/2 to Gnd
485.0 7.00 3.50 425.0
512.0 15.00 1.00 4.20
540.0 1.50
kHz k1/2 V V kHz kHz kHz
Verify SYNCOUT = SYNCIN, RLOAD = 2k1/2 to Gnd Max. Low SYNC Rej. Frequency Verify SYNCOUT = FCLK when RLOAD = 2k1/2 to Gnd. Min. High SYNC Rej. Frequency Verify SYNCOUT = FCLK when RLOAD = 2k1/2 to Gnd. SYNCIN Input Threshold Functional Testing Voltage Verify FCLK from 1.0V to 2.8V. Main PWM Clock Pulse (GBD) - CLPH1 Width One Shot Pulse Width Aux PWM Clock Pulse (GBD) -CLPH2 Width One Shot Pulse Width
555.0 340.0
690 0.90 1.85 2.90
V
80.0 80.0
100.0 100.0
120.0 120.0
ns ns
s Bias Supply Error Amplifier Output Low Voltage Output High Voltage Output High Source Current
VSS > 12.6V. Measure OAOUT voltage when sinking 1.0 mA. VSS < 11.4V. Measure OAOUT voltage when sourcing 150A. VSS < 11.4V. Measure OAOUT source current when OAOUT = 0.5V. 3
43.0 4.55 150.0 4.75 225.0
85.0
mV V
300.0
A
CS5106
Electrical Characteristics: TJ = -40C to 125C, VSS = 9 to 16V, V5REF ILOAD = 2mA, SYNCOUT Free Running, unless otherwise specified. For All Specs: UVSD=6V, OVSD = 0V, ENABLE = 0V, ILIM(1,2) = 0,VFB(1,2) = 3V,RFADJ = RDLYSET = 27.4k1/2.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
s Bias Supply Error Amplifier: continued Output Low Sink Current VSS > 12.6V. Measure OAOUT sink current when OAOUT = 2.5V. VSS Set Point Adjust VSS until OAOUT goes low. Large Signal Gain (GBD) Unity Gain Bandwidth (GBD) Common Mode Input Range (GBD) s VSS Voltage VSS Reset Voltage Toggle ENABLE between Gnd & VCC, then adjust VSS from 2.0V-0.8V until OAOUT goes high.
3.0 11.60 15.00 1.00
20.0 12.25 1.00
50.0 12.80
mA V V/mV MHz V
2.00
1.00
1.40
1.80
V
s Undervoltage Lockout UVSD Turn On Threshold Voltage UVSD Turn Off Threshold Voltage Hysteresis UVSD Input Bias Current
Adjust UVSD from 4.7V-5.3V until GATE 1, 2 goes high. Adjust UVSD from 5.1V-4.3V until GATE 1, 2 goes low. Turnon - Turnoff Set UVSD=0V. Measure Current out of UVSD lead.
4.80 4.45 0.20
5.00 4.70 0.27 0.20
5.10 4.95 0.40 0.50
V V V A
s Overvoltage Lockout OVSD Threshold Voltage OVSD Input Bias Current s ENABLE & PROGRAM ENABLE Lead Output Current PROGRAM Lead Output Current PROGRAM Threshold Voltage ENABLE Threshold Voltage
Adjust OVSD from 4.7V-5.3V until GATE 1, 2 goes low. Set OVSD=0V. Measure Current out of OVSD lead.
4.85
5.00 0.20
5.15 0.50
V A
Measure current out of ENABLE when ENABLE = 0V. Measure current out of PROGRAM when PROGRAM = 0V. ENABLE = Gnd. Adjust PROGRAM from 1.0V - 1.8V until GATE 1, 2 goes high. PROGRAM = Gnd. Adjust ENABLE from 1.0V - 1.8V until GATE 1, 2 goes high.
100.0 20.0 1.20
266.0 60.0 1.40
500.0 100.0 1.60
A A V
1.20
1.40
1.60
V
s Output Undervoltage Delay OUVDELAY Charging Current OUVDELAY Latchoff Voltage
OUVDELAY Set Current VFB1 Charge Threshold
VFB2 Charge Threshold
Set OUVDELAY = 1V, VFB1 = 4.4V Measure OUVDELAY ICHARGE. Toggle ENABLE between Gnd & VCC, then adjust OUVDELAY from 4.7V - 5.3V until GATE 1, 2, goes low. OUVDELAY = VOCLO + 50mV Measure current into OUVDELAY. VSS=1V. Toggle ENABLE between Gnd & VCC, adjust VFB1 from 3.8V - 4.6V until GATE 1, 2 goes low. VSS = 1V. Toggle ENABLE between Gnd & VCC, adjust VFB2 from 3.8V - 4.6V until GATE 1, 2 goes low. 4
7.50 4.80
10.00 5.00
12.50 5.20
A V
0.50 4.05 4.22
1.00 4.40
mA V
3.90
4.15
4.35
V
CS5106
Electrical Characteristics: TJ = -40C to 125C, VSS = 9 to 16V, V5REF ILOAD = 2mA, SYNCOUT Free Running, unless otherwise specified. For All Specs: UVSD=6V, OVSD = 0V, ENABLE = 0V, ILIM(1,2) = 0,VFB(1,2) = 3V,RFADJ = RDLYSET = 27.4k1/2.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
s Current Limit Circuits ILIM1 Current Limit Threshold Voltage ILIM1 Short Circuit Threshold Voltage ILIM1 Input Bias Current ILIM2 Current Limit Threshold V ILIM2 Short Circuit Threshold Voltage ILIM2 Input Bias Current
Adjust ILIM1 from 1.0V - 1.3V until GATE1 goes low. Adjust ILIM1 from 1.30V - 1.50V until GATE1 skips 2-cycles with reference to SYNCOUT. Set ILIM1=0V. Measure current out of ILIM1 lead. Adjust ILIM2 from 1.0V - 1.3V until GATE2 goes low. Adjust ILIM2 from 1.30V - 1.50V until GATE2 skips 2-cycles with reference to SYNCOUT. Set ILIM 2= 0V. Measure current out of ILIM2 lead.
1.16 1.35
1.24 1.44
1.30 1.51
V V
0.50 1.16 1.35 1.24 1.44
5.00 1.30 1.51
A V V
0.50
5.00
A
s Voltage Feedback Control RAMP1 Offset Voltage RAMP1 Input Bias Current RAMP2 Offset Voltage
RAMP2 Input Bias Current VFB1 Input Impedance VFB2 Input Impedance s Gate1,2,2B Output Voltages GATE1 Low State GATE2 Low State GATE2B Low State GATE2B High State GATE2 High State GATE1 High State
VFB1=0V. Adjust RAMP1 from 0V - 0.3V until GATE1 goes low. Measure VRAMP1. Set RAMP1 = 0V. Measure Current out of RAMP1 lead. VFB2 = 0V. Adjust RAMP2 from 0V-3V until GATE2 goes low. Measure VRAMP2. Set RAMP2 = 0V. Measure Current out of RAMP2 lead. Measure input impedance. Measure Input impedance. VSS = 12V. VCC = VSS - VDON PROGRAM = 0V. Measure GATE1 voltage when sinking 1mA. PROGRAM = 0V. Measure GATE2 voltage when sinking 1mA. PROGRAM = 0V. Measure GATE2B voltage when sinking 1mA. Measure VCC - GATE2B voltage when sourcing 1mA. Measure VCC - GATE2 voltage when sourcing 1mA. Measure VCC - GATE1 voltage when sourcing 1mA.
0.08
0.13 0.50
0.20 5.00 0.20
V A V
0.08
0.13
60.0 60.0
0.50 120.0 120.0
5.00 220.0 220.0
A k1/2 k1/2
0.15 0.18 0.18 1.65 1.65 1.65
0.80 0.80 0.80 2.00 2.00 2.00
V V V V V V
s Propagation Delays ILIM1 Delay to Output GATE1
Measure delay from ILIM1 going high to GATE1 going low. ILIM2 Delay to Output GATE2 Measure delay from ILIM2 going high to GATE2 going low. RAMP1 Delay to Output GATE1 Measure delay from RAMP1 going high to GATE1 going low. RAMP2 Delay to Output GATE2 Measure delay from RAMP2 going high to GATE2 going low. 5
80.0 80.0 80.0 80.0
120.0 100.0 115.0 100.0
ns ns ns ns
CS5106
Electrical Characteristics: TJ = -40C to 125C, VSS = 9 to 16V, V5REF ILOAD = 2mA, SYNCOUT Free Running, unless otherwise specified. For All Specs: UVSD=6V, OVSD = 0V, ENABLE = 0V, ILIM(1,2) = 0,VFB(1,2) = 3V,RFADJ = RDLYSET = 27.4k1/2.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
s GATE 2, 2B Non-Overlap Delay GATE2 Turn-on Delay from GATE2B GATE2B Turn-on Delay from GATE2
Measure delay from GATE2B going low @1.7V to GATE2 going high @1.7V. Measure delay from GATE2 going low @1.7V to GATE2B going high @1.7V.
20.0 20.0
45.0 45.0
70.0 70.0
ns ns
s GATE 1, 2, 2B Rise & Fall Times VSS=12V,VCC=VSS-VDON GATE1 Rise Time Measure GATE1 Rise Time from 90% to 10%. CLOAD = 150pF. GATE1 Fall Time Measure GATE1 Fall Time from 10% to 90%. CLOAD = 150pF. GATE2 Rise Time Measure GATE2 Rise Time from 90% to10%. CLOAD = 50pF. GATE2 Fall Time Measure GATE2 Fall Time from 10% to 90%. CLOAD = 50pF. GATE2B Rise Time Measure GATE2B Rise Time from 90% to10%. CLOAD = 50pF. GATE2B Fall Time Measure GATE2B Fall Time from 10% to 90%. CLOAD = 50pF.
50.0
80.0
ns
30.0 50.0 15.0 50.0 15.0
60.0 80.0 30.0 80.0 30.0
ns ns ns ns ns
Package Lead Description
PACKAGE LEAD # LEAD SYMBOL FUNCTION
1
UVSD
2
OVSD
3 4
V5REF OAM
5 6
OAOUT OUVDELAY
7
ILIM1
8
RAMP1
Undervoltage shutdown lead. Typically this lead is connected through a resistor divider to the main high voltage (VIN) line. If the voltage on this lead is less than 5V then a fault is initiated such that GATE1, GATE2 and GATE2B go low. Overvoltage shutdown lead. Typically this lead is connected through a resistor divider to the main high voltage (VIN) line. If the voltage on this lead exceeds 5V then a fault is initiated such that GATE1, GATE2 and GATE2B go low. 5V reference output lead. Capable of 20mA nominal output. If this lead falls to 4.5V, a fault is initiated such that GATE1, GATE2 and GATE2B go low. Auxiliary error amplifier minus input. This lead is compared to 1.2V nominal on the auxiliary error amp plus lead and represents the VSS voltage divided by ten. Auxiliary error amplifier output lead. Source current 300A max. Output undervoltage timing capacitor lead. If the controlled output voltages of either the main or the auxiliary supply are such that either VFB1 or VFB2 is greater that 4.1V nominal, then capacitor from OUVDELAY to ground will begin charging. If the over voltage duration is such that the OUVDELAY voltage exceeds 5V, then a fault will be initiated such that GATE1, GATE2 and GATE2B will go low. Pulse by pulse over current protection lead for the auxiliary PWM. A voltage exceeding 1.2V nominal on ILIM1 will cause GATE1 to go low. A voltage exceeding 1.4V nominal on ILIM1 will cause GATE1 to go low for at least two clock cycles. Current Ramp Input Lead for the Auxiliary PWM. A voltage which is linear with respect to current in the primary side of the auxiliary trans former is usually represented on this lead. A voltage exceeding VFB1 - 0.13 on RAMP1 will cause GATE1 to go low.
6
CS5106
Package Lead Description: continued
PACKAGE LEAD # LEAD SYMBOL FUNCTION
9
VFB1
10
VSS
Voltage Feedback Lead for the Auxiliary PWM. A voltage which represents the auxiliary power supply output voltage is fed to this lead. A voltage less than RAMP1+0.13 on VFB1 will cause GATE1 to go low. VSS power/feedback input lead. See VCC for description of power operation. In addition, this lead is fed to a divide by ten resistor divider and compared to 1.2V nominal at the positive side of the error amplifier. VCC power input lead. This input runs off a Zener referenced supply until VSS > VCC. Then an internal diode which runs between VSS and VCC turns on and all main power is derived from VSS. Auxiliary PWM gate drive lead. This output normally drives the FET which drives the auxiliary transformer. Ground lead. Synchronous PWM gate drive lead. This output normally drives the FET which drives the main transformer. Synchronous PWM gate drive lead. This output normally drives the FET for the gate drive transformer used for synchronous rectification. Voltage feedback lead for the synchronous PWM. A voltage which represents the main power supply output voltage is fed to this lead. A voltage less than RAMP2+0.13 on VFB2 will cause GATE2 to go low and GATE2B to go high. Current ramp input lead for the synchronous PWM. A voltage which is linear with respect to current in the primary side of the main trans former is usually represented on this lead. A voltage exceeding VFB2 - 0.13 on RAMP2 will cause GATE2 to go low and GATE2B to go high. Pulse by pulse over current protection lead for the synchronous PWM. A voltage exceeding 1.2V nominal on ILIM2 will cause GATE2 to go low and GATE2B to go high. A voltage exceeding 1.4V nominal on ILIM2 will cause GATE2 to go low and GATE2B to go high for at least two clock cycles. GATE2, GATE2B non-overlap time adjustment lead. A 27k1/2 resistor from DLYSET to ground sets the non-overlap time to 45ns nominal. Frequency adjustment lead. A 27k1/2 resistor from FADJ to ground sets the clock frequency to 512kHz nominal. Clock output lead. This is a 50% duty cycle, 1V to 5V pulse whose rising edge is in phase with GATE1. This signal can be used to synchronize other power supplies. Clock synchronization lead. The internal clock frequency can be adjusted +10%, -15% by the onset of positive edges of an external clock occurring on the SYNCIN lead. If the external clock frequency is out side the internal clock frequency by +25%, -35% the external clock is ignored and the internal clock free runs. ENABLE programming input. See ENABLE for programming states. PROGRAM has at least 20A min. of available source current. PWM enable input. If PROGRAM is HIGH then a LOW on ENABLE will allow GATE1, GATE2 and GATE2B to switch. If PROGRAM is LOW then a HIGH on ENABLE will allow GATE1, GATE2 and GATE2B to switch. If ENABLE is left floating, it will pull up to a HIGH level. ENABLE has at least 100A (min) of available source current.
11
VCC
12 13 14 15 16
GATE1 Gnd GATE2 GATE2B VFB2
17
RAMP2
18
ILIM2
19 20 21
DLYSET FADJ SYNCOUT
22
SYNCIN
23 24
PROGRAM ENABLE
7
CS5106
Block Diagram
OUVDELAY OAOUT OAM VSS
A1
+ -
Aux. Error Amp 1.2V +
VCC
5V
V
C2 Output Undervoltage Timer G5
G1 RSFF
R Q
C1 G3
+ -
PROGRAM
1.4V
S
5k P1
+
C4
-
F2
S
- 1.4V
C7
CLK1
VCC
START STOP
V
V5REF RAMP1 VFB1
7.4/6.8V 0.13V + 2R
V V
GATE1
DRIVER
G9
RSFF QR
G10
S
Aux. Current Limit Comparator
CLOCK Skip2B Skip Two Clock Pulses SET
V
G14 Gnd
C16
1.4V
ILIM1
Aux. 2nd Current Threshold Comparator
V
Theory of Application Theory of Operation Powering the IC The IC has one supply, VCC, and one Ground lead. If VSS is used for a bootstrapped supply the diode between VSS and VCC is forward biased, and the IC will derive its power from VSS. The internal logic monitors the supply voltage, VCC. During abnormal operating conditions, all GATE drivers are held in a low state. The CS5106 requires 1.5mA nominal of startup current. Startup Assume the part is enabled and there are no over voltage or under voltage faults present. Also, assume that all auxiliary and main regulated output voltages start at 0V. An 8V, Zener referenced supply is typically applied to VCC. When VCC exceeds 7.5V, the 5V reference is enabled and the OSC begins switching. If the V5REF lead is not excessively loaded such that V5REF < 4.5V nominal, OVREFOKO goes OhighO and ORUN1O will go OhighO, releasing GATE1 from its low state. After GATE1 is released, it begins switching according to conditions set by the auxiliary control loop and the auxiliary supply, VSS begins to rise. When VSS > VCC + V(D1), P1 turns on and ORUN2O goes 8 OhighO, releasing GATE2 and GATE2B from their low state. GATE2 and GATE2B begin switching according to conditions set by the main control loop and the main regulated output begins to rise. See startup waveforms in Figure 1. Soft Start Soft start for the auxiliary power supply is accomplished by placing a capacitor between OAOUT and Ground. The error amplifier has 200A of nominal of source current and is ideal for setting up a Soft Start condition for the auxiliary regulator. Care should be taken to make sure that the soft start timing requirements are not in conflict with any transient load requirements for the auxiliary supply as large capacitors on OAOUT will slow down the loop response. Also, the Soft start capacitor must be chosen such that during start or restart, both outputs will come into regulation before the OUVDELAY timer trips. Soft Start for the main supply is accomplished by charging soft start capacitor C6 through D5 and R7 at start up. After the main supply has come into regulation C6 continues to charge and is disconnected from the feedback loop by D8.
+
-
C17 Main 2nd Current Threshold Comparator
+
-
+
C15
-
CLOCK Skip2B Skip Two Clock Pulses SET
+
Reset Dominant
+
C12
C13 Main Current Limit Comparator
-
-
F4
1.2V
+
RUN1
+
C10
C11 G11
RSFF RQ
-
-
R
Aux.PWM Comparator
Main PWM Comparator
2R R RUN2
V
+
-
VREF=5V
4.5
-
+
VREFOK Comparator
ENABLE VREF
C9 +
CLK2 IFSET
SYNCIN OSC SYNCOUT
IDSET
Sync Detection G7
FREQ TOO HIGH
+
1.5V
G8
FREQ TOO LOW
VREFOK
V
-
A2
+
0.13V
F3
G13 C14
DELAY
G12
DRIVER
S
Q
Reset Dominant
+ -
G15 G17
RUN2
DELAY
G16
DRIVER
1.7V
+
V
ILIM2
+
RUN1
G6
RUN 2
VSS
Comparator
C8
-
100k
+
V
Reset TPERIOD Dominant
+
A2
Comparator
-
V
1.4V Over Voltage
+
VSS Restart
Under Voltage Comparator
C5
-
RUN 1
Q
R
G4
ENABLE Comparator
+
D1
45k
Set Dominant
Fault Latch RSFF
C3
-
V
+
-
F1
VREFOK
G18
V
ENABLE UVSD
5V
V
OVSD
TFF Q
T1
SYNCIN SYNCOUT DYLSET FADJ RAMP2 VFB2
GATE2
GATE2B
CS5106
Theory of Application: continued
7.5V VCC VREF,VREF(OK),RUN1 CLK1 GATE1 VFB1 RAMP1 VSS > VCC VSS RUN2 CLK2 GATE2 GATE2B VFB2 RAMP2
age comparator has its positive input referenced to 5V while the over voltage comparator has its negative input referenced to 5V. The output of both comparators are ORed at (G4) with the over current and enable inputs. The output of G4 feeds the input to the fault latch (F2). PROGRAM and ENABLE Leads The PROGRAM lead controls the polarity of the ENABLE lead. If the PROGRAM lead is OhighO or floating, the GATE outputs will go low if the ENABLE input is tied OhighO or floating. If the PROGRAM lead is tied low, the GATE outputs will go low if the ENABLE input is tied OlowO. If the part is then enabled after switching the outputs low, the part will restart according to the procedure outlined in the OStartupO section. FAULT Logic If a VREF, UVSD or OVSD fault occurs at any time, G4 resets the fault latch (F2). RUN1 goes low and all gate drivers cease switching and return to their OlowO state. When RUN1 goes low, the output of the auxiliary op-amp (A1) discharges the soft start capacitor and holds it low while RUN1 is low. If the fault condition is removed before the OUVDELAY timer is tripped, the IC will restart the power supplies when VSS < 1.4V. If the OUVDELAY timer trips, the power supply must be restarted as explained in the following section. Output Undervoltage Delay Timer for the Main and Auxiliary Regulated Outputs C7 and C4 are the output under voltage monitor comparators for the auxiliary and main supplies. If a regulated output drops such that its associated VFB voltage exceeds 4.1V, the output undervoltage monitor comparator goes OhighO and the OUVDELAY capacitor begins charging from 0V. A timing relation is set up by a 10A nominal current source, the OUVDELAY capacitor and a 5V fault threshold at the input of C2 (see Figure 2). If any regulated output drops and stays low for the entire charge time of the OUVDELAY capacitor, a fault is triggered and all GATE drivers will go into a low state. Once this fault is triggered, the IC will restart the power supplies only if the OUVDELAY fault is reset and ENABLE or UVSD is toggled while VSS < 1.4V. To reset the OUVDELAY fault, both the VFB inputs must be less than 4.1V. In the application circuit shown, VFB1 is brought low by OAOUT when RUN1 stops the oscillators. VFB2 is brought low when VAUXP bleeds down and the VFB2 opto-isolator is no longer powered.
1000
Figure 1: Startup waveforms.
Voltage and Current Ramp PWM Comparator Inputs (VFB1,2 and RAMP1,2 leads) C10 and C11 are the PWM comparators for the auxiliary and main supplies. The feedback voltage (VFB) is divided by three and compared with a linear, voltage representation of the current in the primary side of the transformer (RAMP). When the output of the feedback comparator goes OhighO, a reset signal is sent to the PWM flip-flop and the GATE driver is driven OlowO. A 130mV offset on the RAMP leads allows the drivers to go to 0% duty cycle in the presence of light loads. Feedback Voltage for GATE1 Driver (VFB1) Typically the output of the auxiliary error amplifier (A1) is tied to VFB1. The VSS output is programmed to 12V by a 10:1 resistive divider on the negative input of the error amplifier and a fixed 1.2V reference on the positive input of the error amplifier. Pulse by Pulse Over Current Protection and Hiccup Mode (ILIM1,2 leads) C12 and C13 are the pulse by pulse current limit comparators for the auxiliary and main supplies. When the current in the primary side of the transformer increases such that the voltage across the current sense resistor exceeds 1.2V nominal, the output of the current limit comparator goes OhighO and a reset signal is sent to the PWM flip-flop and the GATE driver is driven OlowO. C16 and C17 are the second threshold, pulse by pulse current limit comparators for the auxiliary and main supplies. If the current in the primary side of the transformer increases so quickly that the current sense voltage is not limited by C12 or C13 and the voltage across the current sense resistor exceeds 1.4V, the second threshold comparator will trip a delay circuit and force the GATE driver stage to go low and stay low for the next two clock cycles. Undervoltage and Overvoltage Thresholds C5 and C8 are the undervoltage and overvoltage detection comparators. Typically, these inputs are tied across the middle resistor in a three resistor divider with the top resistor to VIN and bottom resistor to Ground. The under voltage comparator has 200mV of built in hysteresis with respect to a direct input on the UVSD lead. The under volt9
100
TIME (ms)
10
1
0.1
0.01 0.1 1 10 100 1000
CAPACITANCE (nF)
Figure 2: OUVDELAY Time vs. OUVDELAY Capacitance
CS5106
Theory of Application: continued FADJ and DLYSET Leads Amplifier A2 and transistor N3 create a current source follower whose output is FADJ. An external resistor from FADJ to ground completes the loop. The voltage across the resistor is set by a buffered, trimmed, precision reference. In this fashion, an accurate current is created which is used to charge and discharge an internal capacitor thereby creating an oscillator with a tight frequency tolerance. For FADJ resistor value selection, see Figure 3. Transistor N2 is in parallel with N3 and is used to created an independent current across the resistor from DLYSET to ground. This current is used to program the GATE non-overlap delay blocks in the main PWM drivers. For DLYSET resistor value selection, see Figure 4.
1100 1000 900 800
trollers (master). See Figure 5 for the relationship between SYNC, CLK, and GATE waveforms.
SYNCIN CLK1 GATE1 CLK2 SYNCOUT GATE2 GATE2B
Figure 5: SYNC, GATE and CLOCK waveforms.
SYNCIN and SYNCOUT Leads Multiple supplies can be synchronized to one supply by using the SYNC leads. The SYNCIN and SYNCOUT pulses are always 180 degrees out of phase. The SYNCIN input is always in phase with the clock signal for the main driver and the SYNCOUT output is always in phase with the clock signal for the auxiliary driver. If the IC is being used as a slave, the incoming frequency must be within +10%, -20% of the programmed frequency set by its own FADJ resistor. If the frequency on the SYNCIN lead is outside the internal frequency by +25%, -35%, the SYNCIN input will be ignored. If the SYNC signal stops while the power supplies are in synchronized operation, the synchronized supplies will stop and restart free running. If the SYNCIN signal drifts out of frequency specification while the power supplies are in synchronized operation, the synchronized supplies will begin to free run without restarting. Slope Compensation DC-DC converters with current mode control require slope compensation to avoid instability at duty cycles greater than 50%. A slope is added to the current sense waveform (or subtracted from the voltage waveform) that is equal to a percentage (75% typical) of the down slope of the inductor current. In the application diagram shown, the bootstrap (flyback) transformer inductance can be chosen so that the duty cycle never exceeds 50% and therefore does not require slope compensation. The buck indicator in the forward converter would typically be chosen to work in continuous conduction mode with a maximum duty cycle of 50-60% and would require slope compensation. Slope compensation is accomplished as follows: R9 and C9 form a ramp waveform rising each time GATE 2 turns on. C9 is discharged through D3 to the same level each cycle regardless of duty cycle. R10 and R11 are chosen to control the amount of slope compensation. C10 provides filtering for noise and turn-on spikes. To calculate the required slope compensation, calculate the buck indicator down current and the corresponding voltage slope at the current sense resistor - R12. The buck inductor down slope is: Inductor_Slope = 10 VOUT + VQ5 A s L1(H)
Frequency (kHz)
700 600 500 400 300 200 100 0 0 10 20 30 40 50 60 70 80
Resistance kW
Figure 3: SYNCOUT Frequency vs. FADJ Resistors
80 70 60 50 40 30 20 10 0
Time (ns)
0
5
10
15
20
25
30
35
40
45
50
Resistance (kW)
Figure 4: GATE Non-Overlap Time vs. DLYSET Resistance
Oscillator The oscillator generates two clock signals which are 180 degrees out of phase with respect to time. One clock signal feeds the main driver and the other feeds the auxiliary driver. Because the drivers are never turned on at the same time, ground noise and supply noise is minimized. The clock signals are actually 100ns pulse spikes. These spikes create a narrow driver turn-on window. This narrow window prevents the driver from spurious turn on in the middle of a clock cycle. The oscillator can be synchronized by an external clock (slave) or drive the clocks of other con-
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CS5106
Theory of Application: continued The equivalent down slope at the current sense resistor for this application circuit is: NST2 NPT3 V Slope @ R12 = Inductor_Slope NP NS R12 s T2 T3
70
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Time (ns)
60 50 Rise Time 40 Fall Time 30
After choosing R9 and C9 to generate a ramp with a time constant of about 5 times the oscillator period, R10 and R11 can be chosen for the voltage at RAMP2 to be 1.75 of the voltage across R12. Synchronous Rectification Synchronous rectification was chosen to reduce losses in the forward converter. Improvements in efficiency will be most significant in low voltage, medium and high current converters where improvement in conduction loss offsets any added losses for gate drive. In the application circuit Q4 is turned on and off by the forward transformer. Q5 is turned on and off through pulse transformer T4 and the gate driver formed by Q6 and Q7. Because Q4 and Q5 are driven through different types of components, differences in propagation delay must be considered. The DLYSET resistor should be chosen to avoid shoot-through or excessive off time. Gate Drive Capability All GATE drive outputs have nominal peak currents of 0.5A. See Figures 6 and 7 for typical rise and fall times.
20
10
0 50 200 500 1000 1500 2000
Load Capacitance (pF)
Figure 7: Typical GATE1 switching times.
70
60
50
Rise Time
Time (ns)
Design Considerations The circuit board should utilize high frequency layout techniques to avoid pulse width jitter and false triggering of high impedance inputs. Ground plane(s) should be employed. Signal grounds and power grounds should be run separately. Portions of the circuit with high slew rates or current pulses should be segregated from sensitive areas. Shields and decoupling capacitors should be used as required. Special care should be taken to prevent coupling between the SYNC leads and the surrounding leads. Depending on the circuit board layout and component values, decoupling capacitors or reduction in resistor values might be required to reduce noise pick-up on the FADJ and DLYSET resistors. Decoupling capacitors or active pull-up/down might be required to prevent false triggering of the ENABLE and PROGRAM leads.
40
30
20 Fall Time 10
0 50 100 200 500 1000 2000
Load Capacitance (pF)
Figure 6: Typical GATE2, 2B switching times.
11
CS5106
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA
D Lead Count 24 Lead SSOP Metric Max 8.50 Min 7.90 English Max .335 Min .311
Thermal Data RQJC RQJA typ typ
24 Lead SSOP 23 117 uC/W uC/W
SSOP (SW); 5.3mm Body
8.20 (.323) 7.40 (.291) 5.60 (.220) 5.00 (.197) 1.88 (.074) 1.62 (.064) 0.38 (.015) 0.22 (.009)
0.20 (.008) 0.09 (.004)
See DETAIL A
0.65 (.026) BSC
2.13 (.084) MAX Parting Line DETAIL A 1.03 (.041) 0.77 (.030) REF: JEDEC MO-150 Seating Plane D
0.25 (.010) 0.05 (.002)
Ordering Information
Part Number CS5106LSW24 CS5106LSWR24
Rev. 10/27/98
Description 24 Lead SSOP 24 Lead SSOP (tape & reel) 12
Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information.
(c) 1999 Cherry Semiconductor Corporation

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